Electronic equipment (such as, for example, television sets, other audio/video equipments, mobile telephones and personal computers) may nowadays commonly be implemented using digital technology instead of analog technology. It may be both easier and cheaper to design digital systems than analog systems. Further, it may be possible with digital technology to achieve bandwidth reductions and to apply data compression (which may reduce the necessary storage area) and error correction coding (which may yield better signal quality). The more advanced the digital applications get, the more demanding the task of converting an analog signal to a digital signal becomes. Digital video is one example of such a demanding application. For example, digital video may require a very high sampling frequency (e.g. up to around 330 MHz) and/or very high resolution (e.g. up to around 12 bit).
Analog-to-digital converters (A/D converters or ADCs) in general are well known in the art as well as their basic functionality (sample-and-hold, quantization). As the required sampling frequency increases it may be necessary to use ADC structures comprising several constituent ADCs to be able to accommodate the high sampling frequency. Examples of such ADC structures are pipe-lined ADCs and time-interleaved ADCs (e.g. a parallel successive ADC). As an example, U.S. Pat. No. 5,585,796 discloses a time-interleaved ADC for A/D converting a high-frequency analogue signal into a series of digital signals with a high sampling rate. Another example of a time-interleaved ADC is disclosed in EP 0 798 864 B1 and in WO 92/01336 A1.
FIG. 1 illustrates an example time-interleaved ADC 100. The time-interleaved ADC 100 comprises a plurality of constituent ADCs 101, 102, 103, each of which is fed an analog signal as shown at 110. Each of the constituent ADCs may perform conventional ADC operations (sample-and-hold, quantization).
A sample clock 120 controls, via a suitable number of delay elements 122, 123, the sampling phase of each of the constituent ADCs, such that the plurality of constituent ADCs 101, 102, 103 operates cyclically on the analog signal. The time-interleaved ADC 100 also comprises a multiplexer (MUX) 130 that combines the results from the plurality of constituent ADCs to a single data stream.
In this way, a higher sampling frequency may be maintained than what would have been possible with one of the constituent ADCs. If there are M constituent ADCs, then the sampling frequency may be increased by a factor of M.
FIG. 2 schematically illustrates an example video signal 200. The example video signal 200 may, for example, be used as the analog signal input 110 to the example time-interleaved ADC 100 of FIG. 1.
The example video signal 200 comprises information-bearing portions 211, 212, and portions 221, 222, 223 having a reference signal level 220. The information-bearing portions of the video signal should reside in an interval between a black level 230 and a maximum signal level 240. The reference level 220 may or may not be equal to the black level 230.
For proper representation of the video signal on, for example, a screen, it is important that the black level 230 and the maximum signal level 240 are properly controlled during the analog-to-digital conversion of the video signal.
If the black level is not maintained a signal offset results, which may, for example, cause the representation of the video signal to be too bright, too dark, or to have an incorrect bias towards any of the color components (red, blue, green).
If the relation between the maximum signal level and the black level is not maintained a gain offset results, which may, for example, result in the potential signal range not being used to its full potential and/or cause clipping phenomena.
When ADC structures comprising a plurality of constituent ADCs are used, a further problem arises, due to matching imperfections between components of the different constituent ADCs. This means that the gain and offset may vary between the different constituent ADCs. To have a proper representation of the video signal, it is quite important that such mismatch is properly compensated for.
Gain and offset compensation (both overall and per constituent ADC) are thus of importance in time-interleaved ADCs.
An example of offset compensation in a time-interleaved ADC is disclosed in EP 0 798 864 B1 and in WO 92/01336 A1. The disclosed offset compensation requires quite a few analog circuits for its implementation. Further, extra clock cycles are needed to perform the offset compensation, which means that additional constituent ADCs are required to achieve a certain sampling frequency. In EP 0 798 864 B1 and in WO 92/01336 A1, compensation is performed for offset in a respective comparator enclosed within each constituent ADC. Thus, offsets in other parts of the entire (e.g. with reference to an input signal) analog signal chain (such as offset in clamping or in an amplifier preceding the time-interleaved ADC) cannot be compensated for.
An alternative approach to offset compensation is to do the offset compensation in the digital domain. By performing offset compensation in the digital domain, less analog complexity is required. Digital implementations are also more stable and predictable than analog implementations. Furthermore, digital circuits are fully scalable in relation to new and smaller process geometries.
A problem with doing the offset compensation in the digital domain is that the effective signal range decreases after the compensation. If, for example, one of the constituent ADCs is offset compensated by +0.5% and another one of the constituent ADCs is offset compensated by −0.3%, the effective signal range decreases by 0.8%. A decrease in the effective signal range may be detrimental to the performance of succeeding circuitry, as such circuitry may expect a certain effective signal range. Inefficient use of the signal range can also be detrimental to the precision of the representation. Thus, in particular for high definition applications, it may be of importance to obtain an efficient use of the signal range.
For those and other reasons, there is a need for improved methods and arrangements for offset compensation of analog-to-digital converters.